Constraint randomization based question linking to AXI and memory filling
Asic Design Engineer Interview Questions
710 asic design engineer interview questions shared by candidates
I don't remember the question clearly but something that had to do with implementing some methods in a (UVM-like) Scoreboard class.
The first interview asked basic technical questions about logic design, STA and FSM etc. The second one was RTL coding for synchronous FIFO with depth=5
Questions on the resume. SV constructs, FIFO depth, STA questions
All questions were related to my previous experience, testing methodology, and problem solving skills. They also asked some basic oo concepts
Sequence detector with FSM Synchronization Cache
Describe a time when you need to gather information from different sources to troubleshoot an issue.
Write verilog code for D ff.
Describe the projects you have worked on.
write a code to extract input and outputs
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