There are block box modules, and you know nothing about what they are doing, behaior, output, input. Can you create a verification TB for it?
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
What's your name , is it [name] ?
Computer Architecture, Coding in SystemVerilog
Design an FSM for a 2-clock system
What is gray code and 8b10b encoding, and why they are useful
Q. What are all run-phases and in detail discussion about it Q. Basic constraints related to dist, and assertion
Cache Coherency, UVM and TLM related, SV concepts, Past projects.
Memory Consistency
setup/hold time ;verification coverages and types
Q1. FIFO depth, given read and write rates for a burst of x writes Q2. a=0; b=0; c=1; #1 a=c; #1 b =a; (Give waveforms) Q3. a<=0; b<=0; c<=1; #1 a<=c; #1 b< =a; (Give waveforms) Q4. a=0; b=0; c=1; a= #1 c; b=#1 a; (Give waveforms) Q5. a<=0; b<=0; c<=1; a<= #1 c; b<=#1 a; (Give waveforms) Q6. You have incoming bit stream. You can't store them. You get a new bit at every clock edge, find modulo 5 of the updated number everytime. Eg, if bitstream is 10111, you find modulo of 1, then 10, then 101 and so on..
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