Apple SoC Verification Engineer interview questions

Really bad experience. The interviewer take pride in asking stupid tricky questions and seeing candidates getting tricked. They enjoy making fun of you. They are looking for people who can recite the entire SystemVerilog spec instead someone who can do actual work.

I interviewed for Apple , SoC Verification Engineer role at Cupertino for Entry level (MS+0) in March 2024. It's was a 45 mins phone screen Interview. First 15 mins were solely discussed the resue and most recent project (in my case UVM based Verification ) and after that I was asked to code the Scoreboard in uvm or sv. The interview was very nice and supportive. Overall positive experience