Then asks questions in SV & UVM starting from basic concepts to transaction level modelling & even asks you to develop a UVC for a protocol.
Asic Design Engineer Interview Questions
709 asic design engineer interview questions shared by candidates
My projects which was relevant to job role
Asked me questions on Tessent tool
FIFO, clock gating, latches
1. Tell me a little about yourself. 2. What got you interested in FPGAs?
- about SV, FIFO design, arbiter design
what is your salary expectations
Latch and flip flop and rtl design
DCO circuit diagram. analog approach and digital approach
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