fifo design
Asic Engineer Interview Questions
1,076 asic engineer interview questions shared by candidates
how abot time borrowing in Latch,Tell us about clock control and why it can be done
The phone screen with basic questions like your visa status.
Low power design, STA
STA, power analysis and optimization, asynchronous fifo, clock domain crossing,seq detector fsm, counter, other verilog problems, synthesis, minor verification qs, comp arch topics like out of order execution, tomasolu, cache,
I was also asked about why CMOS is used in implementing logic gates. Next, I was about sizing of transistors of a 2 input NAND gate.
The second was about state machine, how to output true for every two consecutive 1s.
The interview was more related to what you wrote in written exam.
Difference Between Associative array and Dynamic Arrya
Swap via value versus reference coding question. Design question about feeding data from producer to consumer (answer uses buffer)
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