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Asic Engineer Interview Questions
1,076 asic engineer interview questions shared by candidates
Design basic logic gates (AND, XOR) using a 2to1 mux. Write a module which will take clk as an input and output a clk divided by 3. Important to note that generated clock needs to be an output of the Flop.
Visually Identify between combinational and squential elements
What are your weekness and how can you surpass them in work environment?
RTL coding related questions such as writing a simple FSM.
How can I estimate a new IP complexity and area without having any specific details yet?
design a trafffic light controller
Qhat is your strength? An example of the time that you take initiative? What is your weakness?
I was asked to write the RTL code for an asynchronous receiver in Verilog
Q. Design a 16X1 MUX using 2X1 mux, How many of need? Q. Many More.
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