state machines, FIFOs sync and non-sync, clock domain crossing, meta stability, buses
Component Design Engineer Interview Questions
163 component design engineer interview questions shared by candidates
Questions regarding hold time violations.
Relocation in Bangalore is possible?
a design was given and an output truth table was asked to find
Q: What is meant by Cache coherency ?
Draw the circuit of a Latch.
1. pattern recognition (fsm -> logic -> code) 2. basic architecture 3. sorting algorithm (how to find a missing number in an array of numbers 4. other simple logic questiosn
Cache Coherency
What is cache? how to enhance its performance? different types of associativity.
Short channel effects, nm CMOS technology limitations, how to retain threshold voltage of MOSFET with decreasing channel length, charge on plates of a capacitor when connected to a voltage source, modeling practical capacitor with ideal elements
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