Phone interviews : CMOS basics, usual some gate/logic using one gate, timing related questions, FIFO depth, max in array, palindrome Onsite : CDC - a lot on various techniques and improvements from one to another, clock MUX logic, Clock dividers, FSM , Timing related question based on designs above
explain briefly about the inverter and its characteristics
- Questions on different types of cache - Difference b/w them - Explain inclusive and exclusive caches
Given an array A[] and a number x, check for pair in A[] with sum as x
Mostly questions on solidwork and they are expecting to good to have experience on solidwork with your current organisation.
Question on your current and past experience mostly.
Why should we pick you instead of others
Asked basic questions based on resume. The position required CPU architecture knowledge. I hadn't taken any of those courses, so interviewer asked only IC designing questoins.
describe the equations for setup time and hold time on a registered path with clock skew
whats the ad and disad of using large cache and small cache
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