Suppose there are two inverters connected back to back. Both are working in 3V domain. What is the output if the input is given as 0V. For the same back to back inverters, if both of them are connected back to back and if both of them are working in 3V domain and if the input is 0V. what is the output.
Check the awareness of applying pre and post randomization in variables in uvm_object.
Digital IC design know how, coding.
Cross clock domain synchronization - Module A transmits @ 100 MHz and Module B accepts at 10 MHz. How will you manage the transactions?
1st two interviewers : Volatile v/s Non Volatile memory (RAM/ROM) Basic Verilog questions like blocking v/s non-blocking, continuous vs procedural etc Explanation of all my FPGA/Verilog-related projects 2:1 MUX using basic gates Setup vs Hold, which is more important, why is it caused. metastability - how to fix it FIFO uses ASIC design flow How does synthesis happen Synchronisation vs Asynchronous clock 3rd Interviewer: Equation for power in a resistor Analysis of parallel LC circuit 2 i/p AND gate where each input is getting pwm of period 10. But on input B, an inverter of 1ms delay is attached. What's the resulting waveform? Is it practical to be used with a f/f Transfer characteristic of NOT gate Can NOT gate be used as an amplifier
Sequence detector
Describe yourself as an engineer.
Write the code for a asyc fifo
SystemVerilog (polymorphism, constraint, assertion), UVM, test plan
How many LUT resources are required to design a 32:1 MUX?
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