Verilog: Difference btw sequantial and combinational logic. Difference btw blocking and non-blocking assignment.
Design Rtl Interview Questions
212 design rtl interview questions shared by candidates
Q: Setup and hold time questions based on the circuit shown.
Q: Define different pipeline hazards.
Protocol specific questions, basics of SV and UVM constructs
Q. Tell me about yourself Q. Built nand gate using 2*1 mux Q. Why mux not called a universal gate and what are the universal gate Q what is setup and hold time Q when setup and hold violation occurs Q. What is pipelining and what is it's drawback Q. On what factors the stage of pipeline depends Q what is the latch up Q what is the difference between latch and flip flop
projects related on cv, low power
Verilog coding rounds - FIFO, arbiters, CDC code, fibonacci sequence, simple logic design codes.
Resume based questions - DMA design, cache, source synchronous protocol, AXI protocol, fabric related questions etc.
Processor peripherals, CSR related questions such as R1C, R1T etc registers, debug, trace and performance event monitoring.
What is metastability? clock domain Crossing questions.
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