FIFO fundamentals (synchronous) and depth calculation, arbiter fundamentals (fixed priority, round robin, weighted), experience with cache, how to optimize a given logic path for timing assuming area is no concern, my ASIC design experience (timing closure, microarchitecture, block explanations).
FIFO depth
nothing as such..everything was from what i had studied in BS and MS
Low power implementation - UPF Level shifters, isolation cells, retention cells, clock gating, PoR sequence etc.
I could not reveal the questions
synchronization of multiple control signals FIFO Depth calculation
sync vs asyc rst
Questions were standard interview question on synthesis and lint
Most questions were from digital electronics and verilog
Design a module to return trigonometric sine value. Other question is related to the designing of the State Machine with the specified requirements.
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