How would you write a test with randomized input (with bounds)?
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Launch 5 (t1,t2,t3,t4,t5) tasks in parallel, wait for 4 of the tasks to be done and kill the task t3.
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Implement Coverage for given scenario
how to balance the pipeline stage to achieve any specific time period?
A question about managing branching methodology when dealing with IP cores.
Compare Superscalar and VLIW processors.
How do u rate in RTRT and ADA
Design scoreboard to compare dut and reference model.
UVM , system verilog and scoreboars related questions.
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