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Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
How to derive circuit diagram for finite state machine.
NOC : one side we have 3 AHB masters, 1 APB master and other side 3 APB Slaves, 0x0000_0000 to 0x_1000_0000 1st APB SLAVE 0x_4000_0000 to 0x_8000_0000 2nd slave oxC000_0000 to 0xFFFF_FFFF 3rd slave In addition to above imagine AHB master number 3 and APB master will provide error response for address range oxC000_0000 to 0xFFFF_FFFF. Note AHB master number 1 and 2 can still access address range oxC000_0000 to 0xFFFF_FFFF. Write a top_tb for this design ? What are the coverpoints or bins you can write ? What is difference between functional coverage and code coverage? If functional coverage is there, why code coverage is required?
Verilog code for basic circuits
Questions related to projects mentioned on the resume, Constraint questions, Write the verilog code and testbench for the given system
Verilog based questions and project related questions
1.system Verilog, UVM, Coverage based questions
Explain pg gate sims, few upf concepts
Asyn FIFO and UVM detail Like YOU HAVE TO CODING IT.
The first question was to make from mix the function f=(abc’)’. After this I was asked to build a 4 to 1 mux from 2to1 muxes. Then I was asked about registers and they wanted me to build a FIFO.
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