how to use UVM events and UVM pool
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Setup time and hold time
Microcontroller and processor, and digital circuits
What is meant by code coverage ?
Create a assertion in UVM?
Basic digital, verilog questionscan be answered if you know the concepts well, Sv was totally into randomization , coverage and assertions. Uvm basic things initial rounds and in depth in last round. In manager round all digital, verilog, sv and uvm were covered
Q: Design d-ff using Mux?
Do you like to document things?
System Verilog and UVM based questions
Are you a team player?
Viewing 281 - 290 interview questions