could you please stop submitting your resume for all the positions
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Questions on my resume (mostly internship based). Basic Computer Architecture questions.
Design a synchronous and asynchronous counter using T-flipflop
why do we need factory registration in UVM testbench
1: what is set up and hold time?
About the skills I have and how that they could use that
what are basic logic gates? design and gate using mux?
1).Questions on array methods. 2).Asked to write scoreboard code in general. 3).Questions on TLM ports.
1. Verification process 2. Test plan 3. UVM and System verilog - logic, coding questions, UVM_Info
Are you willing to work on a shifting schedule?
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