Digital Logic, Computer Architecture, SystemVerilog, UVM, basic PERl
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Questions about debug of failure
Some standard programming questions, hardware and power specific design questions, as well as test philosophy.
Given a 32 bit signal, create a SystemVerilog constraint that ensures that only 2 bits are flipped in randomization.
Give a logic expression to describe the relationship C = A > B
Explain the difference beteween Blocking vs Non-Blocking Assignments.
Typical Scoreboard Structure. What is an Analysis Port?
Basic RTL Design related concepts, SV UVM basic concepts, writing scoreboard.
Question about digital design and system verilog and uvm related questions
1st phone interview: Basics of Verilog. Explanations for different projects on resume. 2D array containing image data, how will you rotate the matrix to rotate the image by 90 degrees clockwise? try to use least memory(i.e) rotate and store in the same input matrix.
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