SystemVerilog (polymorphism, constraint, assertion), UVM, test plan
Design Verification Engineer Interview Questions
950 design verification engineer interview questions shared by candidates
Describe one of your projects done either professionally or academically
Pipelining Hazards?
How do you ensure that your verification test plan provides complete coverage for a complex SoC design, and what steps do you take when coverage goals are not being met?
Gave me a scenario and asked to develop a test plan to best verify the design.
Reverse a Linked List
How do you prevent the reordering of instructions, and how would you use this as a solution to the above issue?
Can you tell me how do you verify your block ?
technical question involves codes and calculations
you should reverse a linked list
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