1. UVM phases and which is task and which is function
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Data Structures questions Bit allocation questions Stack and heap design questions.
Basics of verilog and sv
use non-blocking assignment to implement negative clock triggering SWAP in verilog, read the code
Protocol of Low Power design.
What would I like to work on?
difference between function and task
Digital design verilog etc etc etc
Write Polymorphism code , Project discussion
Almost all questions were about my applied experience on verification. What kind of projects was I involved in. How would I handle a project under stress or time limits.
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