1) Questions were all scenario based and practical .
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
1) What is the difference between virtual and pure virtual functions explain them. 2) What is constructor and destructor 3) Can we override constructor 4) Pseudo code or algorithm to distinguish between even and odd numbers in range of numbers 5)One question on angle between minutes hand and seconds hand something like how much distance traveled (Never expected) 6) What is tuple in python 7) Difference between C++ and Python Some other easy questions.... (Don't remember exactly). I answered most of them but received reject after 2 days.
how to write uvm top
This will be based on your resume they will tell you on which topic they are going to ask when scheduling the interview
Polymorphism, config db.
coding a uvm_driver and interface based on a clk, req, ack, signal set.
How many blocks are in an N way set associate cache?
Questions on constraints and assertions
Designing multiple Gates or some basic logic using Multiplexers. Draw state Diagram & verilog code for 1010 sequence detector.
Questions were from device physics, Analog Design basics like a current mirror, charge pump, LC-VCO, lumped components based circuits, Analog layout, PVT variations effects on basic analog blocks, so on, mostly from my previous work experience.
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