Explain the latest project you undertook.
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
There were no out of the box questions.
What will affect power consumption?
They gave a class - asked to create it's objects and send out random objects in a function.
Design a state machine that will print '1' when a binary string divisible by 5 is input. E.g. '0101', '1111' all must output 1.
Questions on analog designs and filters. Questions on digital designs. Questions on SystemVerilog and Verilog.
Q: How to calculate the depth of FIFO?
Explain how setup time and hold time violations occur and what can be done to reduce there occurence? What is metastability?
Difference between latch and flip flop, Sequence detector design, Divide by n circuits for different values of n. Few scenarios of assertions, Verilog code for positive edge detector and negative edge detector, Setup and Hold time and few codes to debug and provide output. basic questions in digital on mux, questions on code synthesizing
UVM, SystemVerilog and PCIe protocol
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