Explain about UVM and how its work
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Asked about project work mentioned on your resume in depth. Asked about post increment and pre increment question in C++. Asked Polymorphism, OOP concepts in C++. Asked about non blocking and blocking statements in SystemVerilog.
Coding questions - Python - sort a list and check if number is palindrome Logic puzzle Behavioral questions based on previous work experience
C++ coding for LRU policy in cache memory design
Phone screens: Computer Architecture (Virtual memory, Out of order execution, Hazards in a processor) Digital Logic (hardware for bit manipulation, synthesis, Verilog constructs) Programming (OOPS concepts, Data structures) Onsite: Logic Design: Verilog coding, Latches, Clock Gating Programming: OOPS, Perl, hardware modeling Verification: Verification environment, test plan, coverage Architecture: Tomasulo Algorithm, Virtual memory
Integer to Roman question on Leetcode.
Difference between blocked and non blocked.
STA Digital design FSM Sequential circuits etc..
About the coverage closure activity in verification.
what is clock domain crossing?? How we can avoid it? most of the questions related to my resume.
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