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Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Describe what a memory array looks like, what a sense amp generally does, and what an equilibration circuit does.
How do you construct a NOR gate only from NAND gates?
-Protocol Basics -Logic Gates -Design Projects [Verilog] -Verification Projects [SystemVerilog], UVM Fundamentals -C, C++ -OOP -Data Structures
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
All questions were related to my previous experience, testing methodology, and problem solving skills. They also asked some basic oo concepts
bitmasking using systemverilog C++ classes
Constraint randomization based question linking to AXI and memory filling
How to design a UVM testbench for a given design. What all componets are needed etc. Corner cases to test out and efficient way to build environment
Resume centric, cache coherence and consistence, rtl design and verification.
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