Questions about debug of failure
Design Verification Interview Questions
1,115 design verification interview questions shared by candidates
power integrity understanding: including impedance threshold define and theory.
What is the difference between task and function
Design a bitstream pattern detection finite state machine in the HDL of your choice.
Self-assessment, technical skills and soft skills
1. FSM to check if a number is divided by 5. 2. Implement basic logic gates using a MUX and NAND. 3. Reverse a linked list. 4. Questions about a FIFO
pipeline processor architecture, hazard, shared memory problem, cache issues—remote repeated words both in SystemVerilog. I answered how to do it in python, but he insisted Con using c or SystemVerilog. In the last question, he asked me why I choose design verification. The whole procedure lasts about 53 minutes, quite tense I would say. I did not answer the memory coherence and delete repeat words in C. I would say I did not do it well. Hoping this could help others to get job. Just preparing questions.
Memory allocation
described in the interview process.
How do you access a register and confirm it is 12 bit or not?
Viewing 521 - 530 interview questions