What is the difference between task and function
Design Verification Interview Questions
1,115 design verification interview questions shared by candidates
How do you access a register and confirm it is 12 bit or not?
FIFO, LIFO in Verilog
How to have accurate testing when you a large test case to cover.
Explain the structure of uvm verification environment.
Describe Yourself, project related question.
1. Difference between inter assignment and intra assignment delay 2. Blocking and Non- blocking procedural block 3. How to design AND gate using MUX 4. Signals used in FIFO. 5. Do FIFO required address or not? 6. What do you understand by synchronous and asynchronous circuit. 7. How can we disable the randomisation ? 8. Why we use virtual interface in verification environment? 9. How to select and give in the particular testcase which were generated in generator block?
Where do you see yourself in 5 years?
Lcm, Swap, Factorial for C coding Write constraints in system verilog
It gets very technical ranging from Electrical fundamentals to RF fundamentals and then they start to dig deep on each aspect. Know your chip caps really well! I was asked questions on smith charts, imedance matching, typical RF receiver/transmitter systems, signal integrity issues, characteristics of RF amps. As far as behavioral questions were concerned - challenges faced in your last project, how did u solve it and what would your ex boss say about you if I asked him for a reference.
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