Q: How to calculate the depth of FIFO?
Design Verification Interview Questions
1,114 design verification interview questions shared by candidates
Explain how setup time and hold time violations occur and what can be done to reduce there occurence? What is metastability?
Difference between latch and flip flop, Sequence detector design, Divide by n circuits for different values of n. Few scenarios of assertions, Verilog code for positive edge detector and negative edge detector, Setup and Hold time and few codes to debug and provide output. basic questions in digital on mux, questions on code synthesizing
UVM, SystemVerilog and PCIe protocol
write constraint for memory system
Resume - past experiences and projects
He asked me about Data hazards, Instruction sets , Examples of branch prediction , 32 bit adder design. WAR and RAW Instruction examples. Basic Computer architecture questions.
All the questions were pretty basic and were related to fundamentals of logic design and verification.
Describe how CAM (content addressable memory) works.
Know everything in c++. Virtual functions/class. Polymorphism. Be ready to write code on the spot
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