if the inverter's input is connect to its output. how the output voltage curve should be like
Ingeniero Asic Interview Questions
1,076 ingeniero asic interview questions shared by candidates
In technical interview, they asked: (1) about yourself (2) where did you hear the company (3) explain fundamentals regarding electronic elements e.g. diode, bjt, fet, opamp, capacitors (4) college thesis (5) what should they expect from you
Verilog tasks and functions, FSM Design, FIFO Depth, some system verilog questions.
blocking and non-blocking
Where do you see yourself in five years.
What should be the size if it is receiving data and also loosing some packets ?
-Make a AND/OR gate out of muxes -Count the number of 1's in a 7 bit number using only full adders
QUestions were very simple like given a program whats is the output, phases in UVM, implementimg gates using muxes etc.
1.Inverted temperature effect on STA. the question was based on temperature effects on delay below 65nm technology. how STA works under those conditions at different corners. 2. An interesting question about how latency affects jitter. 3. Maximums kew allowed when lock up latches are used. 4. OCV n questions based on it. 5. CRPR. 6. how does a cell get min n max delay? 7. spef file contents, questions about star-rd extractor working. 8. Internship exp based questions.
FIFO questions
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