Question related to FSMs, which diagram describes the implementation better.
Ingeniero Asic Interview Questions
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Full adder code, Gave some verilog codes to debug and find errors, Digital questions and Aptitude is important
what is setup time and hold time
Introduction. Describe the working and the ranges of a transistor.
Questions about experience and some logical quizzes
questions on cmos logic on basic ec topics like lpf hpf chara etc...
How to synchronize a data bus, which has no control. Interviewer was basically trying to poke at the approach to solve that problem. Write clock domain has a burst rate of 80 writes per 100 clocks. Read clock domain reads at a rate of 8 data words in 10 clocks. Data Buffer sizing to not cause overflow Asked to design a 2 request arbiter.
Different ways of modeling FSM in Verilog Use of Casex in Verilog Coding Verilog coding was asked for many counters Timing diagrams of some Digital elements
How to create an interface based on an example DUT
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