Digital Systems such as multiplexers, logic gates
Ingeniero Asic Interview Questions
1,076 ingeniero asic interview questions shared by candidates
What will affect power consumption?
1st round had 5 questions: 1. Some questions on basic digital design like design a NAND/NOR gate using MUX. 2. 1 basic scripting question. 3. Sequence detector FSM question. 4. Fibonacci series..with and without recurring function.
Your'e given a matrix MxN of 0's and 1's. everytime you encounter 1 cell, you need to put 0's in the rows and columns.
Logic puzzles and design/FSM questions related to hardware
They gave a class - asked to create it's objects and send out random objects in a function.
Intro and things worked on. Then he asked me deep about the project I was working on. Synchronous FIFO question. Wrote for 50 continuous cycle s in any 100 cycles but reading every alternate cycles. Depth reqd? How to design synch fifo ? How async fifo ? Is it possible to write and read from sync FIFO built using single port sram in same clock cycle ? Setup time and why we need it ? How will multiply by 63 ? Optimize way of finding the square of a number ? 1, 4, 9, 16, 25,
How do you overcome CDC issues? Detailed questions on each method
all about resume, STA, DFT, Pipelining
Personal research, DVFS, CDC, metastable, asynchronous FIFO, synchronizer, level shifter, clock gating, power gating, dynamic power, leakage power.
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