some kind of high speed protocol and aske me to desgin in verilog
Ingeniero Asic Interview Questions
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Scripting questions on 2D hashes and asked for coding in perl/python. Basic questions on STA
Q.There was a discussion on mealy and moore machine.
And gate using transmission gate
I don't remember the question clearly but something that had to do with implementing some methods in a (UVM-like) Scoreboard class.
The first interview asked basic technical questions about logic design, STA and FSM etc. The second one was RTL coding for synchronous FIFO with depth=5
Design a MUX using only NOT, AND and OR gates
What is clock domain crossing?
1. linked list 2. setup and hold problems 3. fsm for a particular sequence 4. stuck @ fault 5. circuit design for given waveform 6. verilog coding 7. project related questions 8. edge detector circuit 9. finding number of trailing zeroes in a factorial 10. reverse of a string 11. 3 black cap and 2 white cap puzzle 12. system verilog related questions 13. diff b/w blocking and non-blocking statements 14. basics should be strong
Questions on the resume. SV constructs, FIFO depth, STA questions
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