SV constraint writing UVM TB writing
Senior Design Engineer Interview Questions
1,073 senior design engineer interview questions shared by candidates
I was asked to explain my approach for finding the root cause of a failed linear voltage regulator. They were interested in listening to my thought process.
Digital Design questions, Analog design questions
Why are you looking to change job?
3) Coding ability by giving some scenarios
Familiairity with CAD? Desire to do CAD a lot?
Draw Cmos inverter.What would happen if we swap Pmos and Nmos.What if Nmos is connected to VDD. Questions regarding .lib,LEF, Antenna file content . How do we define rectilinear polygon in LEF.. Multicycle Path calculation for setup and hold . Draw 4 Input NAND Gate using 2 -Input NAND Gate what is index table defined in .lib file. How do we define antenna rules in techfile What are all challenges faced in your recent project. Questions were more from your resume. Any scripting which is hard for you. Tell us more about colored flow.
Current mirror pole and zero?what ratio?
Differential pair and current mirror mismatch concern and tuning
Timing closure. How noise(cross-talk) affect setup/hold? How metal dimension affect timing?
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