Verification of the DUT
Senior Verification Engineer Interview Questions
189 senior verification engineer interview questions shared by candidates
systemverilog basics and UVM basics
They asked about the design verification process, UVM concepts and coverage.
Explain inheritance, polymorphism. Write test bench for sequence detector
Can we override constraints like data members?
Why do we need a virtual interface?
SV, V, UVM, Problem solving, Advanced formal verification based questions, experience based questions
In SystemVerilog: Write the code for stepping through a circular array. Also, how would you initialize a multi-dimensional array?
Various Verilog detailed questions. I had about 3 months experience of Verilog some 8 years ago. I can't remember the details of the questions.
Difference Between Associative array and Dynamic Arrya
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