Skip to contentSkip to footer

Soc Analist Interview Questions

Salaries
Interviews

1,151 soc analist interview questions shared by candidates

STA, CTS, Floor planning, Logic Circuits, PNR 1. What is OCV and derate factors 2. Calculation of setup and hold slack (Given values, Thold, Tsetup, Tlogic, derate factors) 3. How to reduce setup violations and hold violations? 4. Difference between H-tree and Mesh? 5. Techniques to reduce clock power? 6. Low power design techniques 7. What is Multi Bit FF? 8. Draw basic logic gates (And) using NOR (NAND) gates? 9. Crosstalk glitches? 10. Placement of macros questions 11. How to calculate channel spacing between macros/ 12. SRAM design questions 13. Physical only cells- Tap cells, Tie cells use and where do we place them 14. How Delay of a net/cell changes with VDD/ 15. Capacitance and Resistance of wire effects on delay and how to reduce it? 16. How to reduce static, Dynamic, short -circuit power? 17. Where to use LVT, HVT cells? 18. Difference between local skew and global skew? 19. Verilog Coding question- Synchronous and Asynchronous DFF 20. What is the use of End cap cells and Decap cells?
avatar

Soc Physical Design Engineer

Interviewed at Apple

4.1★
Mar 29, 2026

STA, CTS, Floor planning, Logic Circuits, PNR 1. What is OCV and derate factors 2. Calculation of setup and hold slack (Given values, Thold, Tsetup, Tlogic, derate factors) 3. How to reduce setup violations and hold violations? 4. Difference between H-tree and Mesh? 5. Techniques to reduce clock power? 6. Low power design techniques 7. What is Multi Bit FF? 8. Draw basic logic gates (And) using NOR (NAND) gates? 9. Crosstalk glitches? 10. Placement of macros questions 11. How to calculate channel spacing between macros/ 12. SRAM design questions 13. Physical only cells- Tap cells, Tie cells use and where do we place them 14. How Delay of a net/cell changes with VDD/ 15. Capacitance and Resistance of wire effects on delay and how to reduce it? 16. How to reduce static, Dynamic, short -circuit power? 17. Where to use LVT, HVT cells? 18. Difference between local skew and global skew? 19. Verilog Coding question- Synchronous and Asynchronous DFF 20. What is the use of End cap cells and Decap cells?

Program to differentiate even and odd number Draw and explain NOT and NAND gate Draw a stick diagram for NOT gate Find ways to make NAND gate a NOT gate Explain methods of verifying your design, such as DFT Scan path.
avatar

Soc Design Engineer

Interviewed at Intel Corporation

3.9★
Mar 23, 2024

Program to differentiate even and odd number Draw and explain NOT and NAND gate Draw a stick diagram for NOT gate Find ways to make NAND gate a NOT gate Explain methods of verifying your design, such as DFT Scan path.

Viewing 1131 - 1140 interview questions

Glassdoor has 1,151 interview questions and reports from Soc analist interviews. Prepare for your interview. Get hired. Love your job.