SystemVerilog Basic, Didn't touch upon UVM. OOPS Concepts, Virtual keyword etc.,
Soc Engineer Interview Questions
191 soc engineer interview questions shared by candidates
Resume Based Questions SoC design flow State Machine code
1. Static and dynamic power 2. How to fix setup and hold time violation without adjusting clk frequency? 3. Significance of VT 4. Subjects of 1st and 2nd semester in mtech. 5. RTL to GDSII 6. Basics of design for testability.
STATIC TIMING ANALYSIS
Pipeline stages in common computer architecture. Why does it has to be 5 stages? Critical path solving question with 5 cascading xor gates.
design traffic light what main things to consider. sr latch. leadership questions
Write a scoreboard in SV or UVM for simple alu where there is an 8 bit input that is changing value every clock cycle and the output should be equal to sum of previous 5 inputs.
Write a test plan for asynchronous reset flip flop
How transistor works and design logic circuit base on a problem given ?
It was on campus interview what is memory ?? what is usb ?? realize 8*3 encode using 2*1 mux what is difference between latch and flip flop what is setup time and hold time
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