Skip to contentSkip to footer

Validation Engineer Interview Questions

Salaries
Interviews

1,604 validation engineer interview questions shared by candidates

-------Intel,MA.-------------------- 1.Intro about the project and what they are doing currently. 2. Overview of my education and prof skills 3. He stopped before the project, Being an verification engineer he found some bugs in my resume. 4.Moving on, He asked me about the projects and dived deep into it. Design Spec, Test plan, architecture integration. 5. I worked on a RTL project - he asked me to verify it. 6. Testbench setup and the how you verify it. 7. UVM testbench setup. 8. What is reference model and how you use it. 9. In Intel, They used rule based verification. Which I didn't know. He explained why? 10. Trust me I was exhausted at this point. He moved to python to test my coding abilities. 11. I told about my work experience in python and then he said I am not good at python. Ok. 12. The Hustle continues, Computer Architecture - Stages of pipeline. 13. What happens in stall situation in a pipeline. 14. Do we need branch predictor? 15. Types of Hazards 16. Why is coherency required ? 17. What is bus ? 18. What is Exclusive state? 19. What happens when you move from E -> M state? 20. What if two processors try to write the same cache location? 21. If there 4 processor and 4 caches- If P0 & P1 have a S location value, If the P4 trys to write that Location. What will happen? The time is up, He asked you have any question for me....
avatar

Pre Silicon Validation Engineer

Interviewed at Intel Corporation

3.9★
Aug 28, 2020

-------Intel,MA.-------------------- 1.Intro about the project and what they are doing currently. 2. Overview of my education and prof skills 3. He stopped before the project, Being an verification engineer he found some bugs in my resume. 4.Moving on, He asked me about the projects and dived deep into it. Design Spec, Test plan, architecture integration. 5. I worked on a RTL project - he asked me to verify it. 6. Testbench setup and the how you verify it. 7. UVM testbench setup. 8. What is reference model and how you use it. 9. In Intel, They used rule based verification. Which I didn't know. He explained why? 10. Trust me I was exhausted at this point. He moved to python to test my coding abilities. 11. I told about my work experience in python and then he said I am not good at python. Ok. 12. The Hustle continues, Computer Architecture - Stages of pipeline. 13. What happens in stall situation in a pipeline. 14. Do we need branch predictor? 15. Types of Hazards 16. Why is coherency required ? 17. What is bus ? 18. What is Exclusive state? 19. What happens when you move from E -> M state? 20. What if two processors try to write the same cache location? 21. If there 4 processor and 4 caches- If P0 & P1 have a S location value, If the P4 trys to write that Location. What will happen? The time is up, He asked you have any question for me....

1 : What's a strength / weakness of yours? 2.a : draw a circuit that implements the XOR operation using NAND gates 2.b : implement some memory unit (flip flop) for the output of the circuit 2.c : make one of the inputs of this circuit the input of another flip flop and its output the input to the XOR function 2.c.i : I kind of unintentionally prompted a question from them when I asked if the flip flops should be operated by the same or separate clocks. They proceeded to ask me what would happen if it was the latter case. 2.d : discuss what timing constraints you would need to be aware of for this circuit to function 2.e : how would you make the circuit run faster? what if timing constraints weren't met? what you need to do then? 2.f : code this circuit in verilog
avatar

ASIC Validation Engineer

Interviewed at Intel Corporation

3.9★
Jan 18, 2022

1 : What's a strength / weakness of yours? 2.a : draw a circuit that implements the XOR operation using NAND gates 2.b : implement some memory unit (flip flop) for the output of the circuit 2.c : make one of the inputs of this circuit the input of another flip flop and its output the input to the XOR function 2.c.i : I kind of unintentionally prompted a question from them when I asked if the flip flops should be operated by the same or separate clocks. They proceeded to ask me what would happen if it was the latter case. 2.d : discuss what timing constraints you would need to be aware of for this circuit to function 2.e : how would you make the circuit run faster? what if timing constraints weren't met? what you need to do then? 2.f : code this circuit in verilog

Viewing 111 - 120 interview questions

Glassdoor has 1,604 interview questions and reports from Validation engineer interviews. Prepare for your interview. Get hired. Love your job.