They asked logical questions to check how innovative you are
Validation Engineer Interview Questions
1,607 validation engineer interview questions shared by candidates
simple question about RC circuit
most efficient way to sort array in C
Murex,Semaphore,Deadlock memory management in brief.
Different debugging methods
A System under test scenario was described and asked several questions about how would you solle certain issues.
Several behavorial questions.
1. basics of cache coherency, cache architecture 2. Test plan scenario for different machines (ex: vending machine)
Do you have experience in Verilog?
Oops, identifying corner cases for specific designs, Computer Architecture concepts.
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