They asked me digital question which was from gate 2000s model
Verification Design Engineer Interview Questions
953 verification design engineer interview questions shared by candidates
Basics of oops concepts in sv
Design AND gate using MUX.
ASIC Design flow questions, Verilog codings, STA, Clock Tree Sythesis, VLSI, Questions on projects mentioned in Resume.
Cost of ball and bat.
First it was a skype interview after resume shortlist. Second it was in the company itself where there was a written exam consisting of digital, analog, apti and C. Followed by project related interview and some design related question(frequency converter).
differenece between function and task , equality and case equality operator, wire and reg and logic, case and casex and casez, dynamic array and queue, what is mail box
Core Digital Perl, C and UVM Given to solve may circuit problems How to code xor gate with multiplexers.
Draw a count to 5 counter logic circuit.
Given variable vector should be randomised as unique values but without using a system verilog keyword which is generally used
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