General questions in Python, C, Verilog, and SystemVerilog.
Verification Design Engineer Interview Questions
953 verification design engineer interview questions shared by candidates
1. About the company, why apple 2. About projects as per resume-interesting test case, negative test case 3. different types of Hazard and how to avoid those 4. pipelining concept 5. Problem-solving: (using associative array-)how to sort names without repetition
Describe fully how a processor works in as much detail as possible.
what is a uvm agent?
Resume questions, fifo questions, assertions, coverage
First interview: describe a FSM for the result of a sequence of binary input mod 5. Merge sort. Second : C/ verilog coding.
Write a test plan for asynchronous reset flip flop
Online interview: 1. What is polymorphism ? 2. Design a 3 bit shift register in verilog RTL ? 3. For a FIFO design, what kind of assertions will you write(what conditions would you check for proper functioning of the FIFO) ?
introduce yourself and why you want to work at apple
Design, Test plan, SystemVerilog ......
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