Some standard programming questions, hardware and power specific design questions, as well as test philosophy.
Verification Design Engineer Interview Questions
953 verification design engineer interview questions shared by candidates
Given a 32 bit signal, create a SystemVerilog constraint that ensures that only 2 bits are flipped in randomization.
Give a logic expression to describe the relationship C = A > B
Explain the structure of uvm verification environment.
FIFO, LIFO in Verilog
It gets very technical ranging from Electrical fundamentals to RF fundamentals and then they start to dig deep on each aspect. Know your chip caps really well! I was asked questions on smith charts, imedance matching, typical RF receiver/transmitter systems, signal integrity issues, characteristics of RF amps. As far as behavioral questions were concerned - challenges faced in your last project, how did u solve it and what would your ex boss say about you if I asked him for a reference.
1. Difference between inter assignment and intra assignment delay 2. Blocking and Non- blocking procedural block 3. How to design AND gate using MUX 4. Signals used in FIFO. 5. Do FIFO required address or not? 6. What do you understand by synchronous and asynchronous circuit. 7. How can we disable the randomisation ? 8. Why we use virtual interface in verification environment? 9. How to select and give in the particular testcase which were generated in generator block?
Started with self introduction What's your role in project What is constraints Clocking block Modport FIFO Polymorphism
Where do you see yourself in 5 years?
How to have accurate testing when you a large test case to cover.
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