Given a function in C++, describe the intended purpose, what it returns, and fix the code so it actually returns what it is meant to return.
Verification Design Engineer Interview Questions
953 verification design engineer interview questions shared by candidates
test bench architecture tesplan and verification
Design a full adder using MUX
1]fabonassi series, 2]binary tree 3]sorting array without built in functions 4]probablities when randomizing 5] unique constraint.
Configdb? Mailboxes etc
Questions from digital electronics and logical reasoning (Verilog, SV and UVM if u know)
Digital electronics,vhdl, verilog, system verilog
NVME Project How it works?
Q: Can you explain the difference between blocking and non-blocking assignments in SystemVerilog? Q: How would you verify a FIFO design? Q: What is a virtual interface and how do you use it in UVM? Q: How do you handle back-to-back transactions in a UVM sequence? Q: How do you debug a failing assertion in simulation?
what is mailbox why we don't use queue instead of mailbox. what is polymorphism and their uses. what is diff bw trsanction and transfer wrt axi.
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