Basic stuff about Verification and assertions
Verification Design Engineer Interview Questions
953 verification design engineer interview questions shared by candidates
Basic Computer Architecture questions. How to extend a 5 stage pipeline to 6 stages. Effects of doing that etc. A few programming questions.
DV related, protocols, sv, uvm, axi,abp
Write TB for one of the projects from past experience . Describe its features and implement DUT interface connections and build TB on whiteboard .
build a function that get: s - sum of puckets n - number of puckets MIN - minimu value of a pucket MAX - maximum value of a pucket return an array in length n that each pucket have a value between MIN and MAX and the sum of all puckets is s. all puckets are random.
They asked about uvm fundamentals. They were looking for strong uvm experience and asked me to write code for scoreboard, monitor and asked about how to connect them.
There are block box modules, and you know nothing about what they are doing, behaior, output, input. Can you create a verification TB for it?
What's your name , is it [name] ?
Computer Architecture, Coding in SystemVerilog
Design an FSM for a 2-clock system
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