About counters ,flipflops gates ?
Verification Design Engineer Interview Questions
953 verification design engineer interview questions shared by candidates
1) tell me about yourself? 2. started from digital electronics, questions from mux.design 10:1 mux from 3:1 mux.difference between synchronous and asynchronous design ,sequential and combinational circuits. 3.what is blocking and non blocking in verilog. 4.write a vcerilog code for d flipflop for asynchronous reset 5.write a verilog code for counter. 6.test bech for the above codes. 7.can we write always block inside initial and vise versa?(no procedural block can be implemented inside another procedural block) 8.how to implement always block function without using always block? 9.what is logic,reg,wire data types and their default value?signed and unsigned data types and their size. 10. simple aptitude problem on clock 8.
1.Introduction about yourself 2.Questions related to sv,uvm 3.Questions related to protocols 4.Coding skills
Mainly about the projects with respect to both theoretical and technical knowledge. Along with it, some SV and UVM related questions like constraints, coverages, semaphore etc
Digital logic and C programming questions
They mostly concentrated on sv , uvm
Regarding Technical skills I don't have any difficulties and regarding job location to change from Bangalore can be difficult
Write the VHDL or Verilog code for a given state machine diagram.
A basic testplan scenario
what is the flow of UVM methodology, and structural view of verification ?
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