Name all the ROB entries in Tomasulo
Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
Basic RTL Design related concepts, SV UVM basic concepts, writing scoreboard.
Question about digital design and system verilog and uvm related questions
1st phone interview: Basics of Verilog. Explanations for different projects on resume. 2D array containing image data, how will you rotate the matrix to rotate the image by 90 degrees clockwise? try to use least memory(i.e) rotate and store in the same input matrix.
power integrity understanding: including impedance threshold define and theory.
implement 4-2 priority decoder to 16-4.
I can't remember much, but one question was on Finite State Machine for Traffic Lifgt control.
Design an FSM and write Verilog code for an asynchronous fifo
They asked about mu uvm design verification project
Was tested on computer architecture, pipeline, hazards, fsm, uvm basics, writing system verilog test benches for resume projects
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