1]fabonassi series, 2]binary tree 3]sorting array without built in functions 4]probablities when randomizing 5] unique constraint.
Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
1. Write a verilog code to find the clock frequency of the clock. 2. What are semaphores?
Questions from digital electronics and logical reasoning (Verilog, SV and UVM if u know)
1. How would you handle a conflict situation? 2. Are you comfortable asking for help? 3. Describe your ideal manager.
Q: How would you implement a multiplication function using only ADD and JUMP instructions in assembly?
UVM Verilog Verification thinking Logic gates
describe one of ur project
all basics of SV,UVM and project
They asked me about school projects that I have done.
Digital electronics,vhdl, verilog, system verilog
Viewing 1481 - 1490 interview questions