Explain Cache and pipeline, how they work?
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
They asked to code using Verilog.
Given an async fifo, tell the testplan --> complicated fifo with lot of requirements..(writes are done by 3 masters. there is an arbiter).
what is blocking and non blocking?
On projects and sv uvm based Protocol knowledge on what we mentioned in resume
mostly in uvm and sv
Bit Manipulation and bit masking
Q 1 What will happen if you drive different sequence item other than the registered one ?
Mostly on writing the code for driver monitor and scoreboard components
Write system verilog code for Monitor to monitor and check the transactions from memory.
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