10's complement question
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
Written Test : The written test consist of questions from aptitude, digital electronics, electronic circuits, C programming , MPMC and other core subjects related to electronics Round 2, 3 & 4: Interview questions are based on digital electronics, verilog, C programming and other core related concepts Round 5: General HR questions like whether agreeing for bond or not..etc
What is the one thing that you are proud of yourself during the learning process ?
questions were asked from design point of view
How to compute perspective correct texture coordinates when rendering a triangle
job changing purpose; job descriptions; target salary; when available.
A block diagram of a protocol block was given and was asked to write a SystemVerilog transactor code.
Domande legate a quali strategie usare per testare funzionalità di ASIC
Mainly System verilog and uvm bases questions,Set up time hold time How to generate a skewed clock How to do clock domain crossing Create a sequence generator Sorting based alogorithm Questions
how would you delete an object in SV? what happens when you assign a parent to child? Explain UPF and what we can accomplish using it?
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