VTC CMOS?
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
In Randomization , calculate the probability of each of the numbers but on different syntaxes.
Only behavior questions, nothing technical
Past experience Projects and day to day work Some SV UVM questions
Implement a 4-bit counter in SV.
They repeatedly asked about how I handle stress
Design a finite state machine for a specific control scenario and explain your verification approach.
Indepth questions for AXI protocol
Q1: I was asked about the basic working of caches Q2: I was told to explain about virtual memory Q3: I was given a cache configuration and was told to identify if I this can be a VIPT or VIVT cache.
* find if a string is a palindrome
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