do a sub string seach of a string using nested loops
Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
What is a parametrized class?
will i join if my girlfriend is not given an offer from the firm (she got through 2 rounds with me)
Verilog, Systemverilog basics and advanced concepts
Two capacitors connected in parallel charged up in different level and then if voltage measure accross one....what would be the volatge?
They asked me digital question which was from gate 2000s model
1. Protocol Questions which Individual worked on. 2. UVM Phases and what are Bottom up and what are top down ? 3. How System/Processor boots and what are the steps to compile and execute the 'C' Code 4. How to call task inside a function ? 5. Difference between automatic and static variables ? 6. what is the makefile and what are the contents of makefile ? How to run the makefile ?
Basics of oops concepts in sv
Design AND gate using MUX.
Based on your qualification and previous experiences, how do you believe you can contribute to our products development?
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