First round tested around major system verilog ,verilog and UVM concepts
Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
Topics like pipelining & hazards, Cache, Assembly language, VHDL, C, frequncy divider, clock gneration using VHDL are touched in the technical rounds. And a question to explain my project from digital design is asked.
Given variable vector should be randomised as unique values but without using a system verilog keyword which is generally used
digital electronics and verilog
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How would you debug a failing simulation where coverage is not met?
Basic question in SV, UVM, Verilog, Linux
Describe the voltage response of a circuit consisting of a current source in series to a switch and a (capacitor parallel to another switch) when each switch is closed.
Why did you not raise alarm on a certain issue? (I didn't think it was that important, but the interviewer thinks it is very important - again a smile that hints that my team is not doing the right thing, according to him).
Compare Superscalar and VLIW processors.
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