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Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
what is VHDL, Verilog?
They asked me about my projects and SV and UVM, but they also asked some real time verification scenarios.
Basics of Verification , various protocols, project details, protocols I have worked on, SV UVM basics, etc
Question in sv ,digital design, uvm, asked coding in verilog basics async dff, shift register, fifofull and empty condition etc
Write a program in any language
Give me an example of the toughest problem you have solved in verification.
What is capacitor in electronics
A train crosses a platform in 36 secs and a pole in 18 secs and some other data was given and we were required to find the length of the train
we have an array with 99 numbers. one number is miss. how to find him?
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