SV and UVM topics in first round and in second round all about our project experiences.
Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
Write a palindrome program in c language?
Questions will depend upon the designation.
Given a black box and input/output ports and functionality, translate from C to verilog a block of code.
Classes, fork_join, randomization, functional coverage , OOPS
1. Write a code to generate a o/p. every time input is 1'b1 output will get asserted next cycle & output will toggle to 0 only when input toggles. 2. Cache schemes. 3. Concept about Virtual, data structures used in scoreboards.
Code some black box RTL in verilog
Not any in particular
What is the difference between combinational and sequential logic?
1. finding the probability of possible combiations of a radom variable with given constraints. 2. Question related to System Verilog Assertions.
Viewing 521 - 530 interview questions